Title
Nonuniformly quantized min-sum decoder architecture for low-density parity-check codes
Abstract
In this paper, we propose a novel min-sum (MS) decoder architecture using nonuniform quantization schemes for low-density parity-check (LDPC) codes. The finite word-length analysis in implementing an LDPC decoder is a very important factor since it directly impacts the size of memory to store the intrinsic and extrinsic messages and the overall hardware area in the partially parallel LDPC decoder. The proposed nonuniform quantization scheme can reduce the finite word-length while achieving similar performances compared to a conventional quantization scheme. From simulation results, it is shown that the proposed 4-bits nonuniform quantization scheme achieves an acceptable decoding performance unlike a conventional 4-bits uniform quantization scheme. In addition, the hardware implementation for the proposed nonuniform quantization scheme requires smaller area.
Year
DOI
Venue
2008
10.1145/1366110.1366217
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
ldpc code,low density parity check
Computer science,Low-density parity-check code,Decoder architecture,Electronic engineering,Quantization (physics),Soft-decision decoder,Uniform quantization,Decoding methods,Quantization (signal processing)
Conference
Citations 
PageRank 
References 
3
0.49
12
Authors
2
Name
Order
Citations
PageRank
Daesun Oh1745.54
keshab k parhi23235369.07