Paper Info
Title
A design synthesis system for recursive DSP algorithms represented by fully specified flow graphs
Abstract
This paper describes a design synthesis environment which can generate an efficient VLSI layout from a recursive DSP algorithm specified by a graph. The design synthesis environment is divided into three parts: optimal schedule generation, circuit synthesis, and VLSI layout generation (silicon compilation). The scheduler first computes optimality conditions for a given input algorithm and then finds a schedule which satisfies the optimality conditions. We have employed a cyclo-static optimal multiprocessor compiler as a scheduler. The circuit synthesis component translates the optimal schedule into a structural specification, including the control structures, for an circuit realization. In the final part, a VLSI layout is generated from the structural specification. We have chosen the LAGER system for the silicon compilation. This paper illustrates the design synthesis process with complete details of a simple, complete example, a second order Direct Form II IIR filter.
Year
DOI
Venue
1995
10.1007/BF02106822
VLSI Signal Processing
Keywords
Field
DocType
Optimal Schedule,Flow Graph,Circuit Generator,Input Algorithm,Design Synthesis
Graph,Control flow graph,Computer science,Parallel computing,Flow (psychology),Infinite impulse response,Compiler,Theoretical computer science,Multiprocessing,Real-time computing,Recursion,Design synthesis
Journal
Volume
Issue
ISSN
11
1-2
0922-5773
Citations 
PageRank 
References 
0
0.34
8
Authors
2
Name
Order
Citations
PageRank
Hyeong-Kyo Kim111.08
Thomas P. Barnwell, III200.68