Name
Title | ||
|---|---|---|
A Novel Matching Criterion And Low Power Architecture For Real-Time Block Based Motion Estimation |
Abstract | ||
|---|---|---|
In recent years, minimizing the power consumption has become a key issue in the design of portable electronic devices. In this paper, low power architecture which can support the real time motion estimation of video signals is presented. The architecture is based on a binary level matching criterion which performs a bit-wise comparison. The processor level design based on simple combinational logic using the binary level matching criterion has been introduced. Compared with the existing architectures, the proposed architecture delivers higher throughput rate, requires fewer input/output lines, and reduces the total power consumption. |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/ASAP.1996.542807 | ASAP |
Keywords | Field | DocType |
low power architecture,existing architecture,bit-wise comparison,motion estimation,power consumption,binary level,novel matching criterion,processor level design,total power consumption,fewer input,higher throughput rate,real-time block,proposed architecture,real time,videoconference,video compression,hardware,combinational logic,process design,computer architecture,input output | Throughput (business),High-definition video,Computer science,Combinational logic,Real-time computing,Motion estimation,Data compression,Power Architecture,Energy consumption,Binary number | Conference |
ISBN | Citations | PageRank |
0-8186-7542-X | 6 | 1.30 |
References | Authors | |
8 | 2 | |