Name
Abstract | ||
|---|---|---|
Evolvable Hardware (EHW) refers to hardware that can change its architecture and behavior dynamically and autonomously by interacting with its environment. The paper deals with an EHW completely developed on FPGA (Field Programmed Gate Array), with emphasis on the chromosome coding for hardware circuit and operation plat form of GA (Genetic Algorithm). A LUT-based VRC (virtual reconfigurable circuit) implementation of EHW is proposed in this article with the aim to find a general model fitter for evolving large scale circuit system. And a row-column dual decode architecture is adapt to speed up configuration. Moreover, its performance is illustrated with several concrete designs. All modules compilation and simulation are preformed by Altera Quartus II 10.0 and tested on DE2-115 Development Board. Finally, this article puts forward some questions which remain to be solved in the future design of EHW. © 2011 IEEE. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ICNC.2011.6022550 | ICNC |
Keywords | Field | DocType |
chromosome coding,evolvable hardware,genetic algorithm,nios ii,field programmable gate arrays,genetic algorithms,decoding,field programmable gate array,encoding,hardware,fpga | Lookup table,Altera Quartus,Computer science,Field-programmable gate array,Evolvable hardware,Gate array,Computer hardware,Genetic algorithm,Speedup,Reconfigurable computing | Conference |
Volume | Issue | Citations |
4 | null | 3 |
PageRank | References | Authors |
0.43 | 4 | 5 |