Name
Abstract | ||
|---|---|---|
An unified gate-level fault model for interconnect opens and bridges is proposed. Defects are modeled as constrained multiple line stuck-at faults. A novel feature of the proposed fault model is its flexibility to accommodate increasing levels of accuracy. ... |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ETS.2005.1 | European Test Symposium |
Keywords | Field | DocType |
unified gate-level fault model,novel feature,proposed fault model,new soc test architecture,wireless connectivity,multiple line stuck-at fault,radio frequency,integrated circuit design,silicon,integrated circuit,resource partitioning,system performance,spread spectrum communication,signal integrity,system design,system on chip,system testing,network routing,chip,tree structure,control network,scheduling,transceivers | System on a chip,Computer science,Scheduling (computing),System testing,Signal integrity,Systems design,Real-time computing,Electronic engineering,Integrated circuit design,Tree structure,Integrated circuit | Conference |
ISBN | Citations | PageRank |
0-7695-2341-2 | 1 | 0.36 |
References | Authors | |
6 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dan Zhao | 1 | 188 | 15.29 |
| Shambhu J. Upadhyaya | 2 | 781 | 69.61 |
| Martin Margala | 3 | 318 | 55.78 |