Paper Info
Title
A 10-b 320-MS/s Stage-Gain-Error Self-Calibration Pipeline ADC
Abstract
A 10-b 320-MS/s pipeline analog-to-digital converter (ADC) with low dc gain opamps, as low as 30.6 dB based on simulations, in its multiplying digital-to-analog converters (MDACs) is presented. A foreground self-calibration technique is proposed to reduce stage gain error by adjusting feedback factor with a calibration capacitor array. The prototype in 90-nm low-power CMOS technology achieves conversion rate of 320 MS/s with peak SFDR and SNDR of 66.7 and 54.2 dB, respectively. The total power dissipation is 42 mW, and it occupies an active chip area of 0.21 mm2 including the calibration circuit. It results in a figure-of-merit (FOM) of 442 fJ/conversion-step. Only 168 clock cycles are used, and no external precise reference sources are needed for the calibration.
Year
DOI
Venue
2012
10.1109/JSSC.2012.2192655
J. Solid-State Circuits
Keywords
Field
DocType
calibration circuit,calibration,analogue-digital conversion,multiplying digital-to-analog converter,calibration capacitor array,stage-gain-error self-calibration pipeline adc,operational amplifiers,foreground self-calibration technique,power 42 mw,figure-of-merit,low-gain opamp,low-power electronics,feedback factor,dc gain opamp,stage gain error reduction,size 90 nm,analog-to-digital converter,cmos digital integrated circuits,stage gain,low-power cmos technology,mdac,pipeline analog-to-digital converter,digital-analogue conversion,self-calibration,chip,capacitors,low power electronics,figure of merit,gain,pipelines,accuracy,least squares approximation
Capacitor,Computer science,Control theory,Spurious-free dynamic range,Converters,Electronic engineering,CMOS,Chip,Electrical engineering,Calibration,Operational amplifier,Low-power electronics
Journal
Volume
Issue
ISSN
47
6
0018-9200
Citations 
PageRank 
References 
8
0.58
9
Authors
5
Name
Order
Citations
PageRank
Chien-Jian Tseng1131.14
Hung-Wei Chen215116.28
Wei-Ting Shen380.58
Wei-Chih Cheng4111.08
Hsin-shu Chen59316.12