Title
Empowering a helper cluster through data-width aware instruction selection policies
Abstract
Narrow values that can be represented by less number of bits than the full machine width occur very frequently in programs. On the other hand, clustering mechanisms enable cost- and performance-effective scaling of processor back-end features. Those attributes can be combined synergistically to design special clusters operating on narrow values (a.k.a. Helper Cluster), potentially providing performance benefits. We complement a 32-bit monolithic processor with a low-complexity 8-bit Helper Cluster. Then, in our main focus, we propose various ideas to select suitable instructions to execute in the data-width based clusters. We add data-width information as another instruction steering decision metric and introduce new data-width based selection algorithms which also consider dependency, inter-cluster communication and load imbalance. Utilizing those techniques, the performance of a wide range of workloads are substantially increased; Helper Cluster achieves an average speedup of 11% for a wide range of 412 apps. When focusing on integer applications, the speedup can be as high as 22% on average.
Year
DOI
Venue
2006
10.1109/IPDPS.2006.1639350
Rhodes Island
Keywords
Field
DocType
helper cluster,average speedup,32-bit monolithic processor,new data-width,data-width information,narrow value,data-width aware instruction selection,performance benefit,low-complexity 8-bit helper cluster,processor back-end feature,wide range,clustering algorithms,resource allocation,resource management,microarchitecture,microcomputers,decoding
Resource management,Cluster (physics),Computer science,Parallel computing,Instruction selection,Resource allocation,Decoding methods,Cluster analysis,Microarchitecture,Speedup,Distributed computing
Conference
ISBN
Citations 
PageRank 
1-4244-0054-6
1
0.35
References 
Authors
18
4
Name
Order
Citations
PageRank
Osman S. Unsal157555.65
Oguz Ergin242425.84
Xavier Vera355230.31
Antonio González43178229.66