Title
Hardware design considerations for edge-accelerated stereo correspondence algorithms
Abstract
Stereo correspondence is a popular algorithm for the extraction of depth information from a pair of rectified 2D images. Hence, it has been used in many computer vision applications that require knowledge about depth. However, stereo correspondence is a computationally intensive algorithm and requires high-end hardware resources in order to achieve real-time processing speed in embedded computer vision systems. This paper presents an overview of the use of edge information as a means to accelerate hardware implementations of stereo correspondence algorithms. The presented approach restricts the stereo correspondence algorithm only to the edges of the input images rather than to all image points, thus resulting in a considerable reduction of the search space. The paper highlights the benefits of the edge-directed approach by applying it to two stereo correspondence algorithms: an SAD-based fixed-support algorithm and a more complex adaptive support weight algorithm. Furthermore, we present design considerations about the implementation of these algorithms on reconfigurable hardware and also discuss issues related to the memory structures needed, the amount of parallelism that can be exploited, the organization of the processing blocks, and so forth. The two architectures (fixed-support based versus adaptive-support weight based) are compared in terms of processing speed, disparity map accuracy, and hardware overheads, when both are implemented on a Virtex-5 FPGA platform.
Year
DOI
Venue
2012
10.1155/2012/602737
VLSI Design
Keywords
Field
DocType
hardware overhead,hardware design consideration,reconfigurable hardware,high-end hardware resource,stereo correspondence algorithm,computationally intensive algorithm,hardware implementation,sad-based fixed-support algorithm,stereo correspondence,edge-accelerated stereo correspondence algorithm,processing block,popular algorithm
Hardware implementations,Computer science,Algorithm,Field-programmable gate array,Embedded computer vision,Computer hardware,Reconfigurable computing
Journal
Volume
ISSN
Citations 
2012,
1065-514X
1
PageRank 
References 
Authors
0.37
25
2
Name
Order
Citations
PageRank
Christos Ttofis1625.90
Theocharis Theocharides220526.83