Name
Title | ||
|---|---|---|
FULLY UTILIZED AND REUSABLE ARCHITECTURE FOR FRACTIONAL MOTION ESTIMATION OF H.264/AVC |
Abstract | ||
|---|---|---|
In this paper, we contributed a new VLSI architecture for frac- tional motion estimation of H.264/AVC. Seven inter-related loops extracted from complex procedure are analyzed and two decom- posing techniques are proposed to parallelize the algorithm for hardware with regular schedule and full utilization. The proposed architecture, also characterized by reusable feature, can support situations in different specification, multiple standards, fast algo- rithm and some cost considerations. H.264/AVC baseline profile Level 3 with complete Lagrangian mode decision can be realized with 290K gates at operating frequency of 100MHz. It is an use- ful Intellectual Property (IP) design for platform based multimedia system. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1109/ICASSP.2004.1327034 | ICASSP (5) |
Keywords | Field | DocType |
scheduling algorithm,intellectual property,hardware,video compression,very large scale integration,vlsi,logic design,parallel algorithm,motion estimation,parallel algorithms,algorithm design and analysis,frequency,data compression | Logic synthesis,Signal processing,Mathematical optimization,Computer science,Parallel algorithm,Scheduling (computing),Image processing,Real-time computing,Motion estimation,Data compression,Very-large-scale integration,Computer engineering | Conference |
Citations | PageRank | References |
67 | 5.83 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tung-Chien Chen | 1 | 791 | 78.22 |
| Yu-Wen Huang | 2 | 1116 | 114.02 |
| Liang-Gee Chen | 3 | 3637 | 383.22 |