Name
Abstract | ||
|---|---|---|
The sequential minimal optimization (SMO) algorithm has been extensively employed to train the support vector machine (SVM). This work presents an efficient application specific integrated circuit chip design for sequential minimal optimization. This chip is implemented as an intellectual property core, suitable for use in an SVM-based recognition system on a chip. The proposed SMO chip was tested and found to be fully functional, using a prototype system based on the Altera DE2 board with a Cyclone II 2C70 field-programmable gate array. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/TVLSI.2011.2107533 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
cyclone ii,specific integrated circuit chip,proposed smo chip,field-programmable gate array,altera de2 board,svm-based recognition system,sequential minimal optimization,efficient application,prototype system,sequential minimal optimization algorithm,vlsi design,intellectual property core,learning artificial intelligence,algorithm design and analysis,minimisation,integrated circuit design,optimization,support vector machine,vlsi,chip,application specific integrated circuit,field programmable gate array,system on a chip,support vector machines,very large scale integration,field programmable gate arrays,intellectual property,algorithm design,kernel | Algorithm design,Computer science,Support vector machine,Field-programmable gate array,Algorithm,Electronic engineering,Chip,Application-specific integrated circuit,Gate array,Sequential minimal optimization,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
20 | 4 | 1063-8210 |
Citations | PageRank | References |
16 | 0.75 | 23 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ta-Wen Kuan | 1 | 37 | 6.59 |
| Jhing-fa Wang | 2 | 982 | 114.31 |
| Jia-Ching Wang | 3 | 515 | 58.13 |
| Po-chuan Lin | 4 | 47 | 5.73 |
| Gaung-Hui Gu | 5 | 22 | 1.85 |