Name
Abstract | ||
|---|---|---|
Scan is a widely used DFT technique to improve test and diagnosis quality. However, failures on scan chain itself account for up to 30% of chip failures. In this paper, a SAT-based technique is proposed to generate patterns to diagnose four types of timing faults in scan chains. The proposed method can efficiently generate high quality diagnostic patterns while achieving high diagnosis resolution. Further more, the computation overhead of equivalent faults proving is reduced. Experimental results on ISCAS'89 benchmark circuits show that the proposed method can reduce at least 70% diagnostic patterns' volume and 60% CPU time compared with other works |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/ISCAS.2012.6271756 | 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012) |
Keywords | Field | DocType |
engines,sat,computer architecture,boolean satisfiability,automatic test pattern generation,controllability,decoding | Stuck-at fault,Automatic test pattern generation,Fault coverage,CPU time,Computer science,Algorithm,Scan chain,Electronic engineering,Chip,Real-time computing,Decoding methods,Computation | Conference |
Volume | Issue | ISSN |
null | null | 0271-4302 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Da Wang | 1 | 0 | 0.34 |
| Lunkai Zhang | 2 | 72 | 6.00 |
| XU Wei-Zhi | 3 | 36 | 8.65 |
| FAN Dong-Rui | 4 | 222 | 38.18 |
| Fei Wang | 5 | 241 | 51.35 |