Name
Abstract | ||
|---|---|---|
Working with low frequency Universal Charge Recovery Logic (CRL) based NAND gate given in [1], the leakage current results in gradual charge up of the output node resulting in an incorrect output. A better implementation of the same circuit which increases the output resistance for the leakage current is used to mitigate this drawback in this paper. Also an analysis of the effect of rise time of clock edge on power dissipation of the Split Charge Recovery Logic (SCRL) based NAND gates has also been done. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/ARTCom.2009.158 | ARTCom |
Keywords | Field | DocType |
universal charge recovery logic,output node,nand gate,leakage current result,clock edge,better implementation,output resistance,scrl gates,improved implementation,split charge recovery logic,leakage current,ultra low power,incorrect output,nand,crl,energy recovery,vlsi design,low frequency,adiabatic,low power electronics,data mining,power dissipation,time frequency analysis,logic gates | Logic gate,Leakage (electronics),Computer science,Dissipation,Rise time,NAND gate,NAND logic,Signal edge,Electrical engineering,Low-power electronics | Conference |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Amit Agarkhed | 1 | 0 | 0.34 |
| Sharvil Patil | 2 | 28 | 4.73 |
| Anu Gupta | 3 | 8 | 3.99 |