Name
Abstract | ||
|---|---|---|
Although many real-world signals are known to follow standard models, signals are usually first sampled, rather wastefully, at the Nyquist rate and only then parametrized and compressed for efficient transport and analysis. Compressed sensing (CS) is a new technique that promises to directly produce a compressed version of a signal by projecting it to a lower dimensional but information preserving domain before the sampling process. Designing hardware to accomplish this projection, however, has remained problematic and while some hardware architectures do exist, they are either limited in signal model or scale poorly for low power implementations. In this paper, we design, implement and evaluate CapMux, a scalable hardware architecture for a compressed sensing analog front end. CapMux is low power and can handle arbitrary sparse and compressible signals, i.e. it is universal. The key idea behind CapMux's scalability is time multiplexed access to a single shared signal processing chain that projects the signal onto a set of pseudo-random sparse binary basis functions. We demonstrate the performance of a proof-of-concept 16-channel CapMux implementation for signals sparse in the time, frequency and wavelet domains. This circuit consumes 20µA on average while providing over 30dB SNR recovery in most instances. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/IGCC.2012.6322255 | Green Computing Conference |
Keywords | Field | DocType |
scalable analog front end,low power,signals sparse,scalable hardware architecture,pseudo-random sparse binary basis,real-world signal,16-channel capmux implementation,hardware architecture,arbitrary sparse,signal model,compressible signal,single shared signal processing,sparse matrices,frequency domain analysis,compressed sensing,wavelet transforms,sampling methods,cs,sensors,switches,hardware,nyquist rate,capacitors | Signal processing,Analog front-end,Computer science,Real-time computing,Computer hardware,Multiplexing,Nyquist rate,Compressed sensing,Scalability,Hardware architecture,Wavelet | Conference |
ISBN | Citations | PageRank |
978-1-4673-2153-2 | 3 | 0.42 |
References | Authors | |
12 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zainul Charbiwala | 1 | 150 | 12.93 |
| Paul D. Martin 0001 | 2 | 71 | 4.74 |
| Mani Srivastava | 3 | 13052 | 1317.38 |