Name
Abstract | ||
|---|---|---|
This paper presents an error compensation method for fixed-width group canonic signed digit (GCSD) multipliers that receive a W-bit input and generate a W-bit product. To efficiently compensate for the truncation error, the encoded signals from the GCSD multiplier are used for the generation of the error compensation bias. By Synopsys simulations, it is shown that the proposed method leads to up to 84% reduction in power consumption and up to 78% reduction in area compared with the fixed-width modified Booth multipliers. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transinf.E93.D.1497 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
fixed-width, GCSD multiplier, quantization error, digital arithmetic | Truncation error,Round-off error,Computer science,Arithmetic,Algorithm,Multiplier (economics),Error detection and correction,Quantization (signal processing),Integrated circuit,Power consumption | Journal |
Volume | Issue | ISSN |
E93D | 6 | 1745-1361 |
Citations | PageRank | References |
1 | 0.37 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yong-Eun Kim | 1 | 16 | 4.96 |
| Kyung Ju Cho | 2 | 72 | 11.76 |
| Jin-Gyun Chung | 3 | 169 | 28.63 |
| Xin-ming Huang | 4 | 356 | 46.91 |