Name
Abstract | ||
|---|---|---|
As fabrication process technology continues to advance, mask set costs have become prohibitively expensive. Structured ASICs can offer price and performance between ASICs and FPGAs. They are attractive for mid-volume production and offer good intellectual property security. In this paper, a structured ASIC methodology, where 2 metal- and 1 via-mask are customised, is described. The CAD tools are fully compatible with conventional ASIC design flows and a comparison of area and delay performance with ASICs and FPGAs is given. A prototype structured ASIC implementing an LED-backlit LCD controller was fabricated in a 0.13 μm CMOS process. It was verified and power consumption compared with an ASIC design. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1109/FPT.2010.5681422 | Field-Programmable Technology |
Keywords | Field | DocType |
CMOS integrated circuits,application specific integrated circuits,field programmable gate arrays,industrial property,integrated circuit design,masks,ASIC design,CAD tools,CMOS process,LED-backlit LCD controller,fabrication process technology,intellectual property security,mask set costs,power consumption,size 0.13 mum,structured ASIC methodology | Logic gate,Mask set,Control theory,Computer science,Field-programmable gate array,CMOS,Application-specific integrated circuit,Integrated circuit design,Power consumption,Embedded system | Conference |
ISBN | Citations | PageRank |
978-1-4244-8980-0 | 1 | 0.34 |
References | Authors | |
12 | 8 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sam M. H. Ho | 1 | 8 | 1.83 |
| Steve C. L. Yuen | 2 | 49 | 9.26 |
| Hiu Ching Poon | 3 | 1 | 1.02 |
| Thomas C. P. Chau | 4 | 53 | 6.81 |
| Yanqing Ai | 5 | 11 | 2.25 |
| Philip H.W. Leong | 6 | 849 | 101.45 |
| Oliver Chiu-sing Choy | 7 | 23 | 7.83 |
| Kong-pang Pun | 8 | 315 | 55.34 |