Name
Title | ||
|---|---|---|
A Delay Model Of Multiple-Valued Logic Circuits Consisting Of Min, Max, And Literal Operations |
Abstract | ||
|---|---|---|
Delay models for binary logic circuits have been proposed and clarified their mathematical properties. Kleene's ternary logic is one of the simplest delay models to express transient behavior of binary logic circuits. Goto first applied Kleene's ternary logic to hazard detection of binary logic circuits in 1948. Besides Kleene's ternary logic, there are many delay models of binary logic circuits, Lewis's 5-valued logic etc. On the other hand, multiple-valued logic circuits recently play an important role for realizing digital circuits. This is because, for example, they can reduce the size of a chip dramatically. Though multiple-valued logic circuits become more important, there are few discussions on delay models of multiple-valued logic circuits. Then, in this paper, we introduce a delay model of multiple-valued logic circuits, which are constructed by Min, Max, and Literal operations. We then show some of the mathematical properties of our delay model. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1587/transinf.E93.D.2040 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
multiple-valued logic, multiple-valued logic circuits, hazard detection, delay model | Logic synthesis,Diode–transistor logic,Digital electronics,Sequential logic,Pass transistor logic,Logic optimization,Computer science,Algorithm,Resistor–transistor logic,Logic family | Journal |
Volume | Issue | ISSN |
E93D | 8 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shinichi Takagi | 1 | 3 | 9.69 |
| N. Ohnishi | 2 | 469 | 96.96 |