Name
Abstract | ||
|---|---|---|
In this paper, we propose a soft IP generator which can add or remove PCM codec modules arbitrarily. It can be applied to PCM codec IP designs that need to change their related modules, corresponding to different working environments. It also can help us to easily manage our soft IP modules, produce optimized modules, and remove unnecessary modules, in order to reduce the implementation cost. In addition, users can implement their own Verilog HDL code of PCM codec by following our predefined interface specification, and integrate it with our optimal PCM codec module to produce the users' own optimized system. |
Year | DOI | Venue |
|---|---|---|
2002 | 10.1109/FPT.2002.1188700 | FPT |
Keywords | Field | DocType |
logic cad,implementation cost reduction,codecs,pulse code modulation,hardware description languages,vlsi cad tools,circuit optimisation,industrial property,pcm codec optimization,vlsi,circuit cad,integrated circuit design,soft ip generator,verilog hdl code,pcm codec modules,interface specification | Pulse-code modulation,Soft IP,Computer science,Integrated circuit design,VHDL,Verilog,Very-large-scale integration,Codec,Hardware description language,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7803-7574-2 | 1 | 0.39 |
References | Authors | |
5 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gwo-Yang Wu | 1 | 1 | 0.39 |
| Liang-Bi Chen | 2 | 26 | 18.40 |
| Yuan-Long Jeang | 3 | 10 | 5.44 |
| Gwo-Jia Jong | 4 | 59 | 18.97 |