Name
Title | ||
|---|---|---|
The Rom Design With Half Grouping Compression Method For Chip Area And Power Consumption Reduction |
Abstract | ||
|---|---|---|
In memory design, the issue is smaller size and low power. Most power used in the ROM is consumed in lien capacitance such as address lines. Word lines, bit lilies. and decoder. This paper presents ROM design of a novel HG (Half Grouping.) compression method so a, to reduce the si, parasitic capacitance Of bit lilies and the area of the row decoder for power consumption and chip area reduction. ROM design result of 5 12 point FFT block shows that the proposed method reduces 40.6% area, 42.12% power. and 37.81% transistor number respectively in comparison with the conventional method. The designed ROM with proposed method is implemented ill a 035 mu m CMOS process. It consumes 5.8 mW at 100 MHz with a single 3.3 V power supply. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transele.E92.C.352 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | DocType | Volume |
ROM, HG (Half Grouping), memory | Journal | E92C |
Issue | ISSN | Citations |
3 | 0916-8524 | 0 |
PageRank | References | Authors |
0.34 | 2 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ki-sang Jung | 1 | 0 | 0.34 |
| Kang-jik Kim | 2 | 0 | 0.34 |
| Young-Eun KIM | 3 | 0 | 0.34 |
| Jin-Gyun Chung | 4 | 169 | 28.63 |
| Kihyun Pyun | 5 | 6 | 3.25 |
| Jong-Yeol Lee | 6 | 70 | 10.83 |
| Hang-geun Jeong | 7 | 0 | 0.34 |
| Seong-Ik Cho | 8 | 65 | 6.84 |