Name
Abstract | ||
|---|---|---|
Dynamic voltage and frequency scaling (DVFS) has become a primary means for achieving power efficiency on many processor architectures. However, traditional DVFS techniques cannot provide tight performance guarantees while scaling the clock frequency. We present an elegant, theoretical approach to stochastically characterize workloads. Based on load characterization, a systematic feedback control design methodology is developed that leads to stochastic minimization of performance loss. It is demonstrated that our load-aware stochastic approach is able to significantly reduce processor power consumption while delivering a performance guarantee that is much tighter than what it is achievable with classical feedback controller. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/VLSI-SoC.2012.6379035 | VLSI-SOC |
Keywords | Field | DocType |
microcontrollers,load regulation,systematic feedback control design methodology,stochastic processes,dynamic voltage and frequency scaling,power efficiency,stochastic minimization,processor architecture,control system synthesis,tight performance guarantee,load-aware stochastic feedback control,feedback,clocks,performance loss,processor power consumption reduction,dvfs,minimisation,scaling clock frequency,stochastic programming,control theory,quality of service,application software,real time systems,hardware,digital tv,transform coding | Electrical efficiency,Computer science,Control theory,Stochastic process,Control engineering,Minimisation (psychology),Minification,Frequency scaling,Load regulation,Stochastic programming,Clock rate | Conference |
ISSN | ISBN | Citations |
2324-8432 | 978-1-4673-2656-8 | 0 |
PageRank | References | Authors |
0.34 | 0 | 2 |