Name
Abstract | ||
|---|---|---|
This paper presented a simplified hardware architecture of the block cryptographic algorithm, HIGHT, for wireless applications like a RFID system. We have modified the original HIGHT algorithm that reduced the critical path in the key scheduler and dismissed redundant logics sharing encryption and decryption datapathes, and thereby yield a smaller silicon area. The proposed HIGHT supporting both encryption and decryption had 2,608 gates, 13% smaller than the original HIGHT design excluding decryption block. It consumes the average power 10.8 mu W at 2.5 V for 100 kHz. It can be applicable to passive RFID tag without serious difficulty in size and power. Also, the maximum clock frequency of 125 MHz allows a data throughput rate of 235 Mbps that can support cryptography of high-speed multimedia data. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/elex.6.180 | IEICE ELECTRONICS EXPRESS |
Keywords | Field | DocType |
block cipher, RFID, security, cryptic circuit, ubiquitous | Block cipher,Computer science,Embedded system | Journal |
Volume | Issue | ISSN |
6 | 4 | 1349-2543 |
Citations | PageRank | References |
3 | 0.44 | 1 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Young-Il Lim | 1 | 18 | 4.66 |
| Jehoon Lee | 2 | 37 | 9.61 |
| Younggap You | 3 | 26 | 7.97 |
| Kyoung-Rok Cho | 4 | 217 | 31.77 |