Title
Performance And Complexity Evaluation Of Otr-Uwb Receiver
Abstract
This article presents a new transmitted reference UWB receiver, which utilizes the orthogonal property of even and odd order derivatives of Gaussian pulses in neighboring chips for synchronization. This system, referred to as orthogonal TR-UWB (OTR-UWB), employs only a single spreading code, which results in much lower mean detection time compared to DS-UWB systems. The hardware complexity for OTR-UWB receiver is significantly reduced against conventional TR-UWB systems. In addition, simulation results show that BER performance is improved, while the new system is capable of supporting higher data rates. Also, this article presents the FPGA implementation of OTR-UWB, with a bit-rate of 25Mb/s without using equalizer. In addition, we present the DSP algorithm of baseband. Hardware of this system is implemented on two different FPGAs from ALTERA and XILINX, CycloneII (EP2C35F672C6) and Spartan 3 (3s4000fg676-5). Gate estimation and power analysis are performed by Quartus II 7.2 (ALTERA) and ISE 8.1 (XILINX) softwares.
Year
DOI
Venue
2009
10.4018/jitn.2009070104
INTERNATIONAL JOURNAL OF INTERDISCIPLINARY TELECOMMUNICATIONS AND NETWORKING
Keywords
Field
DocType
Acquisition, DS-UWB, FPGA, OTR-UWB, UWB
Power analysis,Equalizer,Synchronization,Baseband,Spartan,Hardware complexity,Computer science,Field-programmable gate array,Real-time computing,Gaussian
Journal
Volume
Issue
ISSN
1
3
1941-8663
Citations 
PageRank 
References 
0
0.34
9
Authors
3
Name
Order
Citations
PageRank
Hossein Gharaee1156.47
Abdolreza Nabavi24717.09
Jalil Etminan300.34