Name
Abstract | ||
|---|---|---|
Directory-based and bus-based cache coherence schemes are defined and described. Directory-based schemes can be classified as centralized or distributed. Both categories support local caches to improve processor performance and reduce traffic in the interconnection. Schemes using presence flags, B pointers, and linked lists are discussed. Bus-based systems provide uniform memory access to all processors. This memory organization allows a simpler programming model, making it easier to develop new parallel applications or to move existing applications from a uniprocessor to a parallel system. Two architectural variations of bus-based systems are described: multiple-bus and hierarchical architectures. |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/2.55502 | IEEE Computer |
Keywords | DocType | Volume |
Bus-based system,Directory-based scheme,bus-based cache coherence scheme,memory organization,new parallel application,parallel system,uniform memory access,B pointer,architectural variation,hierarchical architecture,Scalable Shared-Memory Multiprocessor Architectures | Journal | 23 |
Issue | ISSN | Citations |
6 | 0018-9162 | 7 |
PageRank | References | Authors |
7.74 | 3 | 10 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shreekant S. Thakkar | 1 | 141 | 59.28 |
| Michel Dubois | 2 | 1303 | 259.66 |
| Anthony T. Laundrie | 3 | 39 | 19.48 |
| Gurindar S. Sohi | 4 | 2655 | 301.82 |
| David V. James | 5 | 39 | 19.48 |
| Stein Gjessing | 6 | 1182 | 99.28 |
| Manu Thapar | 7 | 39 | 11.76 |
| Bruce Delagi | 8 | 32 | 11.90 |
| Michael J. Carlton | 9 | 7 | 8.08 |
| Alvin M. Despain | 10 | 426 | 107.10 |