Name
Title | ||
|---|---|---|
A dual-edged triggered explicit-pulsed level converting flip-flop with a wide operation range |
Abstract | ||
|---|---|---|
In a multiple supply voltage system, the level converters are inserted between two different voltage domains. However, those level converters may cause the propagation delays and power consumption. In order to eliminate the overhead of level conversion, a dual-edged triggered explicit-pulsed level converting flip-flop (DETEP-LCFF) with a wide operation range is proposed. It is composed of a clock pulse generator and a modified differential cascode voltage switch with pass gate (DCVSPG) latch. The clock pulse generator has the symmetric pulse triggering time and holding period helping shorten the D-Q delay. By employed diode-connected PMOS transistors and two NMOS transistor stacked below the diode PMOS transistors, the proposed DETEP-LCFF can be operated from near-threshold region to super-threshold region. It is implemented in TSMC 65nm CMOS technology. It functions correctly across all process corners with a wide input voltage range, from 400mV to 1V. The proposed LCFF has a minimum D-Q delay of 781ps, a setup time of - 610ps, and a power dissipation of 2.3μW when the input voltage is 0.4V. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/SOCC.2013.6749667 | SoCC |
Keywords | Field | DocType |
tsmc cmos technology,dcvspg,switches,diode-connected pmos transistors,dual-edged triggered explicit-pulsed level converting flip-flop,power consumption,convertors,size 65 nm,multiple supply voltage system,low-power electronics,clocks,clock pulse generator,level conversion overhead,cmos logic circuits,time 781 ps,propagation delays,time -610 ps,pulse generators,power 2.3 muw,level converters,flip-flops,mosfet,symmetric pulse triggering time and holding period,voltage 400 mv to 1 v,super-threshold region,modified differential cascode voltage switch with pass gate latch,d-q delay,nmos transistor,detep-lcff,near-threshold region,low power electronics | Clock signal,NMOS logic,Cascode,Computer science,Real-time computing,Electronic engineering,CMOS,Pulse generator,PMOS logic,MOSFET,Electrical engineering,Low-power electronics | Conference |
ISSN | Citations | PageRank |
2164-1676 | 1 | 0.38 |
References | Authors | |
9 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mei-Wei Chen | 1 | 4 | 1.18 |
| Ming-Hung Chang | 2 | 69 | 9.81 |
| Pei-Chen Wu | 3 | 29 | 2.90 |
| Yi-Ping Kuo | 4 | 5 | 1.24 |
| Chun-Lin Yang | 5 | 1 | 0.38 |
| Yuan-Hua Chu | 6 | 99 | 38.56 |
| Wei Hwang | 7 | 254 | 44.40 |