Name
Abstract | ||
|---|---|---|
Streaming network traffic measurement and analysis is critical for detecting and preventing any real-time anomalies in the network. The high speeds and complexity of today's networks, coupled with ever evolving threats, necessitate closing of the loop between measurements and their analysis in real time. The ensuing system demands high levels of programmability and processing where streaming measurements adapt to the changing network behavior in a goal-oriented manner. In this work, we exploit the features and requirements of the problem and develop an application-specific FPGA-based closed-loop measurement (CLM) system. We make novel use of fine-grained partial dynamic reconfiguration (PDR) as underlying reprogramming paradigm, performing low-latency just-in-time compiled logic changes in FPGA fabric corresponding to the dynamic measurement requirements. Our innovative dynamically reconfigurable socket offers 3脳 logic savings over conventional static solutions, while offering much reduced reconfiguration latencies over conventional PDR mechanisms. We integrate multiple sockets in a highly parallel CLM framework and demonstrate its effectiveness in identifying heavy flows in streaming network traffic. The results using an FPGA prototype offer 100 percent detection accuracy while sustaining increasing link speeds. |
Year | DOI | Venue |
|---|---|---|
2014 | 10.1109/TC.2012.228 | Computers, IEEE Transactions |
Keywords | Field | DocType |
application-specific fpga-based closed-loop measurement,fpga fabric,fpga prototype offer,network traffic,network behavior,clm framework,dynamic measurement requirement,conventional pdr mechanism,closed-loop measurements,network traffic measurement,dynamically reconfigurable system,conventional static solution,field programmable gate arrays,registers,hardware,network monitoring,measurement systems,reconfigurable hardware,parallel circuits,programming,logic design,pattern matching | Logic synthesis,Computer science,Parallel computing,Field-programmable gate array,FPGA prototype,Exploit,Real-time computing,Network monitoring,Network traffic measurement,Control reconfiguration,Reconfigurable computing,Embedded system | Journal |
Volume | Issue | ISSN |
63 | 2 | 0018-9340 |
Citations | PageRank | References |
1 | 0.36 | 16 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Faisal Khan | 1 | 1 | 0.36 |
| Soheil Ghiasi | 2 | 352 | 34.74 |
| Chen-Nee Chuah | 3 | 2006 | 161.34 |