Name
Abstract | ||
|---|---|---|
Error diagnosis is becoming more difficult in VLSI circuit designs due to the increasing complexity In this paper, we present an algorithm based on verification for improving the accuracy of design error diagnosis. This algorithm integrates three-valued logic simulation and Boolean satisfiability (SAT). It uses test patterns generated by gate level stuck-at fault ATPG tool for parallel pattern simulation, and uses SAT-based Boolean comparison to enhance the three-valued simulation, in which universally quantified conjunction normal formulas (CNF) represent the unknown constraints in the implementation with black boxes, and need not circuit structural transformation. Our approach can fast and efficiently eliminate many false candidates, experimental results on ISCAS'85 circuits show the accuracy and the speed of this approach. |
Year | Venue | Keywords |
|---|---|---|
2003 | ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS | boolean satisfiability |
Field | DocType | Citations |
Automatic test pattern generation,Boolean circuit,Computer science,Boolean satisfiability problem,Algorithm,Logic simulation,Black box,Very-large-scale integration,Circuit minimization for Boolean functions,And-inverter graph | Conference | 1 |
PageRank | References | Authors |
0.37 | 10 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Guanghui Li | 1 | 4 | 2.51 |
| Ming Shao | 2 | 9 | 1.94 |
| Xinrong Li | 3 | 1266 | 157.76 |