Name
Abstract | ||
|---|---|---|
Recent progress in program analysis has produced tools that are able to compute upper bounds on the use of dynamic memory. This opens up a space for the use of dynamic memory abstraction in high-level synthesis. In this paper, we explain how to design hardware using C programs with malloc() and free(). A compilation process is outlined for transforming C programs with heap operations into a hardware description language. As demonstrated by our experiments, this approach is feasible. Further, automatic parallelization of the generated circuits improves by a factor up to 1.9 in terms of clock frequency and a factor up to 2.7 in terms of clock cycles over the previous work. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1723112.1723125 | FPGA |
Keywords | Field | DocType |
hardware description language,clock frequency,high-level synthesis,automatic parallelization,heap operation,dynamic memory abstraction,compilation process,c program,dynamic memory,clock cycle,upper bound,high level synthesis,program analysis | Dynamic random-access memory,C dynamic memory allocation,Computer science,Parallel computing,High-level synthesis,Heap (data structure),Program analysis,Computer hardware,Clock rate,Automatic parallelization,Hardware description language | Conference |
Citations | PageRank | References |
5 | 0.65 | 12 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jiri Simsa | 1 | 97 | 4.88 |
| Satnam Singh | 2 | 571 | 59.08 |