Name
Abstract | ||
|---|---|---|
This paper presents a high-throughput decoder architecture for generic quasi-cyclic low-density parity-check (QC-LDPC) codes. Various optimizations are employed to increase the clock speed. A row permutation scheme is proposed to significantly simplify the implementation of the shuffle network in LDPC decoder. An approximate layered decoding approach is explored to reduce the critical path of the layered LDPC decoder. The computation core is further optimized to reduce the computation delay. It is estimated that 4.7 Gb/s decoding throughput can be achieved at 15 iterations using the current technology. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/TVLSI.2008.2005308 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
generic quasi-cyclic low-density parity-check,approximate layered decoding approach,computation core,critical path,computation delay,layered ldpc decoder,ldpc decoder,high-throughput decoder architecture,high-throughput layered ldpc decoding,clock speed,current technology,decoding,decoder,error correction code,throughput,routing,very large scale integration,low density parity check,high throughput,hardware,computer architecture,ldpc code | Parity bit,Low-density parity-check code,Computer science,Parallel computing,Electronic engineering,Error detection and correction,Soft-decision decoder,Critical path method,Throughput,Decoding methods,Clock rate | Journal |
Volume | Issue | ISSN |
17 | 4 | 1063-8210 |
Citations | PageRank | References |
25 | 1.32 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiqiang Cui | 1 | 149 | 10.00 |
| Zhongfeng Wang | 2 | 25 | 1.32 |
| Youjian Liu | 3 | 605 | 49.82 |