Name
Abstract | ||
|---|---|---|
The design and implementation of on-chip test functions on the 68040 microprocessor are described. The discussion includes an introduction to the 68040, along with the testability goals and objectives that were set at the beginning of the design. Further discussions detail the different design-for-testability techniques used to control and observe the behavior of the 68040 subsystems. Topics covered include the global test architecture, special test modes for the internal RAM arrays, the scan circuitry used for structural testing of random logic, and the IEEE 1149.1 (JTAG) implementation on the 68040 |
Year | DOI | Venue |
|---|---|---|
1990 | 10.1109/TEST.1990.114091 | Washington, DC |
Keywords | Field | DocType |
computer architecture,integrated circuit testing,integrated memory circuits,logic arrays,logic testing,microprocessor chips,printed circuit testing,production testing,random-access storage,68040 microprocessor,IEEE 1149.1 JTAG,cache test,global test architecture,internal RAM arrays,on-chip test functions,random logic,scan circuitry,scan test,structural testing,testability | Testability,Design for testing,Architecture,Structural testing,Computer architecture,Computer science,Read-write memory,Microprocessor,Electronic engineering,Random logic,Internal RAM | Conference |
Citations | PageRank | References |
11 | 3.44 | 0 |
Authors | ||
8 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Michael G. Gallup | 1 | 30 | 10.14 |
| William Ledbetter Jr. | 2 | 11 | 3.44 |
| Ralph C. McGarity | 3 | 24 | 7.17 |
| Steve McMahan | 4 | 11 | 3.44 |
| Kenneth Scheuer | 5 | 12 | 5.03 |
| Clark G. Shepard | 6 | 11 | 3.44 |
| Lal Sood | 7 | 20 | 6.13 |
| Ledbetter, W., Jr. | 8 | 11 | 3.44 |