Name
Abstract | ||
|---|---|---|
Recent progress in worst case timing analysis of programs has made it possible to perform accurate timing analysis of pipelined execution and instruction caching. However there has not been much progress in worst case timing analysis of data caching. This is mainly due to load/store instructions that reference multiple memory locations such as those used to implement array and pointer based references. These load/store instructions are called dynamic load/store instructions and most current analysis techniques take a very conservative approach to their timing analysis. In many cases, it is assumed that each of the references from a dynamic load/store instruction will miss in the cache and replace a cache block that would otherwise lead to a cache hit. This conservative approach results in severe overestimation of the worst case execution time (WCET). The paper proposes two techniques to minimize the WCET overestimation due to such load/store instructions. The first technique uses a global data flow analysis technique to reduce the number of load/store instructions that are misclassified as dynamic load/store instructions. The second technique utilizes data dependence analysis to minimize the adverse impact of dynamic load/store instructions. The paper also compares the WCET bounds of simple benchmark programs that are predicted with and without applying the proposed techniques. The results show that they significantly (up to 20%) improve the accuracy of WCET estimation especially for programs with a large number of references from dynamic load/store instructions |
Year | DOI | Venue |
|---|---|---|
1996 | 10.1109/RTTAS.1996.509540 | IEEE Real-Time Technology and Applications Symposium |
Keywords | Field | DocType |
multiple memory locations,efficient worst case timing,accurate timing analysis,pointer based references,store instruction,wcet estimation,cache storage,reduced instruction set computing,benchmark programs,data caching,data dependence analysis,cache hit,computational complexity,efficient worst case timing analysis,instruction sets,pipelined execution,wcet overestimation,current analysis technique,timing analysis,global data flow analysis,real-time systems,dynamic load,cache block,dynamic load/store instructions,worst case timing analysis,real time systems,computer aided software engineering,dynamic programming,data analysis,data flow analysis,computer languages,scheduling algorithm,worst case execution time | Pointer (computer programming),Worst-case execution time,Instruction set,Cache,Computer science,Scheduling (computing),Parallel computing,Data-flow analysis,Real-time computing,Static timing analysis,Reduced instruction set computing | Conference |
ISBN | Citations | PageRank |
0-8186-7448-2 | 55 | 7.48 |
References | Authors | |
11 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sung-Kwan Kim | 1 | 97 | 15.23 |
| Sang Lyul Min | 2 | 2212 | 208.29 |
| Rhan Ha | 3 | 587 | 54.88 |