Name
Abstract | ||
|---|---|---|
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operations together. Results on a range of loop accelerators show average energy savings of 32% gained by voltage scaling below the nominal supply voltage. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1145/1391469.1391694 | Anaheim, CA |
Keywords | Field | DocType |
hardware,embedded system,frequency scaling,embedded systems,high level synthesis,registers,hardware accelerator,voltage,power generation,pipelines,computer architecture | Pipeline transport,Chaining,Computer science,Voltage,High-level synthesis,Electronic engineering,Real-time computing,Frequency scaling,Time to market,Rollback,Electricity generation,Embedded system | Conference |
ISSN | ISBN | Citations |
0738-100X | 978-1-60558-115-6 | 9 |
PageRank | References | Authors |
0.68 | 8 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ganesh S. Dasika | 1 | 387 | 24.30 |
| Shidhartha Das | 2 | 997 | 70.00 |
| Kevin Fan | 3 | 335 | 20.29 |
| Scott Mahlke | 4 | 4811 | 312.08 |
| David M. Bull | 5 | 347 | 21.44 |