Title | ||
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Statistical Analysis Of Mapping Technique For Timing Error Correction In Current-Steering Dacs |
Abstract | ||
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Timing errors become dominant in dynamic performance of high-speed and high-resolution current-steering Digital-to-Analog converters (DACs). To improve the dynamic performance and relax the requirements of timing errors in circuit/layout design, a mapping technique, based on on-chip timing error measurement, was proposed. This mapping technique can significantly improve the dynamic performance, no matter if timing errors are interconnection-related or mismatch-related. Matlab simulation results show that the Spurious-free Dynamic Range (SFDR) is improved, e.g. 30dB for linearly distributed interconnection-related timing errors and 10dB for randomly distributed mismatch-related timing errors. |
Year | DOI | Venue |
---|---|---|
2007 | 10.1109/ISCAS.2007.378331 | 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11 |
Keywords | Field | DocType |
error correction,radio frequency,statistical analysis,interconnection,sampling methods,integrated circuit layout,spurious free dynamic range,chip,switches,high resolution | Integrated circuit layout,Page layout,Dynamic range,Computer science,Radio frequency,Spurious-free dynamic range,Electronic engineering,Converters,Error detection and correction,Static timing analysis | Conference |
ISSN | Citations | PageRank |
0271-4302 | 6 | 1.17 |
References | Authors | |
2 | 5 |
Name | Order | Citations | PageRank |
---|---|---|---|
Yongjian Tang | 1 | 37 | 5.04 |
Hans Hegt | 2 | 101 | 17.59 |
Arthur H. M. van Roermund | 3 | 379 | 67.62 |
Konstantinos Doris | 4 | 48 | 10.18 |
Joost Briaire | 5 | 53 | 6.12 |