Paper Info
Title
Use-Based Register Caching with Decoupled Indexing
Abstract
Wide, deep pipelines need many physical registers to hold the results of in-flight instructions. Simultaneously, high clock frequencies prohibit using large register files and bypass networks without a significant performance penalty. Previously proposed techniques using register caching to reduce this penalty suffer from several problems including poor insertion and replacement decisions and the need for a fully-associative cache for good performance. We present novel mechanisms for managing and indexing register caches that address these problems using knowledge of the number of consumers of each register value. The insertion policy reduces pollution by not caching a register value when all of its predicted consumers are satisfied by the bypass network. The replacement policy selects register cache entries with the fewest remaining uses (often zero), lowering the miss rate. We also introduce a new, general method of mapping physical registers to register cache sets that improves the performance of set-associative cache organizations by reducing conflicts. Our results indicate that a 64-entry, two-way set associative cache using these techniques outperforms multi-cycle monolithic register files and previously proposed hierarchical register files.
Year
DOI
Venue
2004
10.1145/1028176.1006724
Proceedings of the 31st annual international symposium on Computer architecture
Keywords
Field
DocType
satisfiability,indexation,register file,indexing,registers,frequency,pollution,knowledge management,pipelines,sequential consistency
Status register,Register allocation,Cache,Computer science,Parallel computing,Control register,Stack register,Memory address register,Register renaming,Processor register
Conference
Volume
Issue
ISSN
32
2
0163-5964
ISBN
Citations 
PageRank 
0-7695-2143-6
22
0.86
References 
Authors
12
2
Name
Order
Citations
PageRank
J. Adam Butts124919.76
Gurindar S. Sohi22655301.82