Title
Run-time power gating of on-chip routers using look-ahead routing
Abstract
Since on-chip routers in Network-on-Chips play a key role in on-chip communication between cores, they should be always preparing for packet injections even if a part of cores are in standby mode, resulting in a larger standby power of routers compared with cores. The run-time power gating of individual channels in a router is one of attractive solutions to reduce the standby power of chip without affecting the on-chip communication. However, a state transition between sleep and active mode incurs the performance penalty, and turning a power switch on or off dissipates the overhead energy, which means a short-term sleep adversely increases the power consumption. In this paper, we propose a sleep control method based on look-ahead routing that detects the arrival of packets two hops ahead, so as to hide the wake-up delay and reduce the short-term sleeps of channels. Simulation results using real application traces show that the proposed method conceals the wake-up delay of less than five cycles, and more leakage power can be saved compared with the original naive method.
Year
DOI
Venue
2008
10.1109/ASPDAC.2008.4484015
ASP-DAC
Keywords
Field
DocType
standby power,larger standby power,power switch,wake-up delay,leakage power,run-time power,on-chip routers,short-term sleep,power consumption,look-ahead routing,on-chip communication,network on chip,pipelines,look ahead,informatics,routing,chip,network on a chip,switches
Standby power,Computer science,Computer network,Real-time computing,Electronic engineering,Network packet,Network on a chip,Look-ahead,Chip,Power gating,Router,Energy consumption,Embedded system
Conference
ISSN
ISBN
Citations 
2153-6961
978-1-4244-1922-7
45
PageRank 
References 
Authors
1.39
8
4
Name
Order
Citations
PageRank
Hiroki Matsutani157662.07
Michihiro Koibuchi272674.68
Daihan Wang3824.78
Hideharu Amano41375210.21