Name
Title | ||
|---|---|---|
40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications |
Abstract | ||
|---|---|---|
This paper presents a high-speed forward error correction (FEC) architecture based on two-parallel Reed-Solomon (RS) decoder for 40-Gb/s optical communication systems. A high-speed two-parallel RS(255,239) decoder has been designed and the derived structure can also be applied to implement the 40-Gb/s RS FEC architecture. The proposed 40-Gb/s RS FEC has been implemented with 0.18-mum CMOS standard cell technology in a supply voltage of 1.8 V and Xilinx Virtex4 FPGA. The implementation results show that 16-Ch. RS-based FEC architecture can operate at a clock frequency of 160 MHz and has a throughput of 41 Gb/s for the Xilinx Virtex4 FPGA. Also RS-based FEC operates at a clock frequency of 400 MHz and has a throughput of 102-Gb/s for 0.18-mum CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/APCCAS.2008.4746164 | APCCAS |
Keywords | Field | DocType |
cmos integrated circuits,reed-solomon codes,bit rate 102 gbit/s,voltage 1.8 v,optical communications,forward error correction,two-parallel reed-solomon decoder,optical communication,xilinx virtex4 fpga,bit rate 40 gbit/s,field programmable gate arrays,decoding,cmos standard cell technology,forward error correction architecture,frequency 160 mhz,error correction,optical communication system,reed solomon,computer architecture,polynomials,throughput | Forward error correction,Computer science,Field-programmable gate array,Error detection and correction,Electronic engineering,Reed–Solomon error correction,CMOS,Decoding methods,Throughput,Clock rate | Conference |
ISBN | Citations | PageRank |
978-1-4244-2342-2 | 4 | 0.56 |
References | Authors | |
5 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Seungbeom Lee | 1 | 45 | 7.04 |
| Hanho Lee | 2 | 205 | 40.92 |
| Changseok Choi | 3 | 33 | 7.39 |
| Jongyoon Shin | 4 | 27 | 2.95 |
| Jesoo Ko | 5 | 27 | 3.96 |