Name
Abstract | ||
|---|---|---|
This paper describes an approach for high-level estimation of area, delay and power for FPGA synthesis. This approach has been integrated within the PACT compiler framework which has an automated design space exploration pass that determines the effects of various compiler optimizations on the synthesized hardware. Such a pass needs early estimation of area, delay and power. Towards this end, we have developed area and delay models for various RTL level operators such as adders, multipliers, and logical operators, which are parameterized with the bit widths of the devices. We have also derived high-level equation based power macro-models which take into account input switching activities, input spatial correlation and input bit width. These models are derived by actual synthesis of the RTL operators using back-end logic synthesis and place-and-route tools. Experimental results show that these area, delay and power models are accurate and efficient. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/968280.968329 | FPGA |
Keywords | Field | DocType |
input spatial correlation,power model,input bit width,power macro-models,power estimation,fpga synthesis,delay model,actual synthesis,account input,high level area,pact compiler framework,back-end logic synthesis,compiler optimization,biology,logic synthesis,reactions,place and route,simulation,reconfigurable hardware,spatial correlation,cell | Logic synthesis,Adder,Computer science,Parallel computing,Field-programmable gate array,Real-time computing,Compiler,Optimizing compiler,Operator (computer programming),Design space exploration,Reconfigurable computing | Conference |
ISBN | Citations | PageRank |
1-58113-829-6 | 1 | 0.41 |
References | Authors | |
1 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tianyi Jiang | 1 | 79 | 6.50 |
| Xiaoyong Tang | 2 | 352 | 20.62 |
| Prith Banerjee | 3 | 255 | 23.94 |