Name
Abstract | ||
|---|---|---|
This paper presents compiler technology that targets general purpose microprocessors augmented with SIMD execution units for exploiting data level parallelism. FFT kernels are accelerated by automatically vectorizing blocks of straight line code for processors featuring two-way short vector SIMD extensions like AMD's 3DNow! and Intel's SSE 2. Additionally, a special compiler backend is introduced which is able to (i) utilize particular code properties, (ii) generate optimized address computation, and (iii) apply specialized register allocation and instruction scheduling. Experiments show that automatic SIMD vectorization can achieve performance that is comparable to the optimal hand-generated code for FFT kernels. The newly developed methods have been integrated into the codelet generator of FFTW and successfully vectorized complicated code like real-to-halfcomplex non-power-of-two FFT kernels. The floating-point performance of FFTW's scalar version has been more than doubled, resulting in the fastest FFT implementation to date. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1007/978-3-540-45209-6_39 | LECTURE NOTES IN COMPUTER SCIENCE |
Keywords | Field | DocType |
instruction scheduling,register allocation,data level parallelism | Instruction scheduling,Register allocation,Computer science,Parallel computing,Microprocessor,SIMD,Vectorization (mathematics),Compiler,Data parallelism,Fast Fourier transform | Conference |
Volume | ISSN | Citations |
2790 | 0302-9743 | 13 |
PageRank | References | Authors |
0.85 | 5 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stefan Kral | 1 | 71 | 9.97 |
| Franz Franchetti | 2 | 974 | 88.39 |
| Juergen Lorenz | 3 | 74 | 9.73 |
| Christoph W Ueberhuber | 4 | 109 | 15.89 |