Paper Info
Title
A high speed and low power 4∶1 multiplexer with cascoded clock control
Abstract
This paper describes two new 4:1 multiplexer (MUX) architectures for high speed and low power graphic memory interface. One is based on the conventional one-stage 4:1 multiplexer and the other is based on the mixed (with tree and one-stage structure) 4:1 multiplexer. Main idea is cascoding one more clock control device in current mode logic (CML) implementation of 4:1 MUX. This added input clock control level plays the same role of AND operation at the output of conventional 4:1 MUX. With this idea, power consumption is drastically decreased about 67% and also 83% respectively, compared to conventional ones, without a loss of speed. The simulation results show that 10Gb/s 4:1 MUXs in proposed architecture consume the current of 1.25mA, 1.9mA respectively, at the supply voltage of 1.8V and have over 280mV of eye openings with 0.18μm CMOS technology.
Year
DOI
Venue
2010
10.1109/APCCAS.2010.5774935
APCCAS
Keywords
Field
DocType
low-power consumption,cmos integrated circuits,cascoded clock control,multiplexing equipment,clock control device,mixed multiplexer,current 1.25 ma,voltage 1.8 v,graphic memory interface,cmos technology,clocks,size 0.18 mum,current 1.9 ma,high speed operation,4:1 multiplexer architecture,4∶1 mux,current mode logic,tin
Memory interface,Clock control,Computer science,Voltage,Electronic engineering,Multiplexer,CMOS,Current-mode logic,Power consumption
Conference
ISBN
Citations 
PageRank 
978-1-4244-7454-7
0
0.34
References 
Authors
2
4
Name
Order
Citations
PageRank
Jin-Hyoung Park1111.77
Ji-Seop Song200.34
Shin-il Lim3810.10
Suki Kim413839.60