Abstract | ||
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This paper proposes dependable routing algorithms for multi-chip NoC platforms. In a multi-chip NoC platform, multiple NoCs are connected via off-chip links, and on-chip networks are seamlessly extended to a multi-chip network. Such platforms have several potential advantages in embedded systems with many cores, such as automotive control systems. One limitation of this approach is that the extended multi-chip network cannot usually preserve the full topology of the on-chip network within the LSI package, due to the limitation of number of pins in the LSI packages. Furthermore, automotive companies require the dependability against a chip fault, where the whole chip becomes faulty, in addition to the normal single component (a router or a link) fault model. This paper discusses two approaches to the dependable routing algorithms for the multichip NoC platforms, and compares their performance through Verilog simulations. |
Year | DOI | Venue |
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2012 | 10.1109/DFT.2012.6378227 | Defect and Fault Tolerance in VLSI and Nanotechnology Systems |
Keywords | Field | DocType |
multi-chip network,multichip noc platform,automotive company,multi-chip noc platform,lsi package,chip fault,on-chip network,extended multi-chip network,automotive application,automotive control system,dependable routing algorithm,clustering algorithms,topology,hardware description languages,system on a chip,network on chip,network routing,logic gates,routing | Dependability,System on a chip,Computer science,Network on a chip,Chip,Router,Verilog,Fault model,Embedded system,Hardware description language | Conference |
ISBN | Citations | PageRank |
978-1-4673-3043-5 | 4 | 0.62 |
References | Authors | |
7 | 2 |
Name | Order | Citations | PageRank |
---|---|---|---|
Tomohiro Yoneda | 1 | 353 | 41.62 |
Masashi Imai | 2 | 36 | 7.63 |