Name
Title | ||
|---|---|---|
Analysis and architecture design of variable block-size motion estimation for H.264/AVC |
Abstract | ||
|---|---|---|
Variable block-size motion estimation (VBSME) has become an important video coding technique, but it increases the difficulty of hardware design. In this paper, we use inter-/intra-level classification and various data flows to analyze the impact of supporting VBSME in different hardware architectures. Furthermore, we propose two hardware architectures that can support traditional fixed block-size motion estimation as well as VBSME with less chip area overhead compared to previous approaches. By broadcasting reference pixel rows and propagating partial sums of absolute differences (SADs), the first design has the fewer reference pixel registers and a shorter critical path. The second design utilizes a two-dimensional distortion array and one adder tree with the reference buffer that can maximize the data reuse between successive searching candidates. The first design is suitable for low resolution or a small search range, and the second design has advantages of supporting a high degree of parallelism and VBSME. Finally, we propose an eight-parallel SAD tree with a shared reference buffer for H.264/AVC integer motion estimation (IME). Its processing ability is eight times of the single SAD tree, but the reference buffer size is only doubled. Moreover, the most critical issue of H.264 IME, which is huge memory bandwidth, is overcome. We are able to save 99.9% off-chip memory bandwidth and 99.22% on-chip memory bandwidth. We demonstrate a 720-p, 30-fps solution at 108 MHz with 330.2k gate count and 208k bits on-chip memory |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/TCSI.2005.858488 | IEEE Trans. on Circuits and Systems |
Keywords | Field | DocType |
h.264/avc,block matching,108 mhz,reference pixel rows,trees (mathematics),video coding technique,integer motion estimation,reference pixel registers,inter-level classification,very large scale integration (vlsi) architecture,motion estimation (me),reference buffer,motion estimation,video coding,intra-level classification,adder tree,variable block-size motion estimation,2d distortion array,variable block size,data flow,hardware architecture,very large scale integration,critical path,hardware,memory bandwidth,partial sums,digital signal processing,chip,bandwidth,low resolution | Block size,Gate count,Memory bandwidth,Adder,Degree of parallelism,Computer science,Electronic engineering,Chip,Critical path method,Motion estimation | Journal |
Volume | Issue | ISSN |
53 | 3 | 1549-8328 |
Citations | PageRank | References |
120 | 6.46 | 15 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ching-Yeh Chen | 1 | 653 | 49.43 |
| Shao-Yi Chien | 2 | 1603 | 154.48 |
| Yu-Wen Huang | 3 | 1116 | 114.02 |
| Tung-Chien Chen | 4 | 791 | 78.22 |
| Tu-Chih Wang | 5 | 386 | 52.77 |
| Liang-Gee Chen | 6 | 3637 | 383.22 |