Title
A FPGA Core Generator for Embedded Classification Systems
Abstract
We describe in this work a Core Generator for Pattern Recognition tasks. This tool is able to generate, according to user requirements, the hardware description of a digital architecture, which implements a Support Vector Machine, one of the current state-of-the-art algorithms for Pattern Recognition. The output of the Core Generator consists of a high-level language hardware core description, suitable to be mapped on a reconfigurable device, like a Field Programmable Gate Array (FPGA). As an example of the use of our tool, we compare different solutions, by targeting several reconfigurable devices, and implement the recognition part of a machine vision system for automotive applications.
Year
DOI
Venue
2011
10.1142/S0218126611007244
JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS
Keywords
Field
DocType
Core generator,pattern recognition,machine learning,Support Vector Machine,field programmable gate array
Machine vision system,Computer science,Support vector machine,Field-programmable gate array,Computer hardware,Digital architecture,User requirements document,Automotive industry,Embedded system
Journal
Volume
Issue
ISSN
20
2
0218-1266
Citations 
PageRank 
References 
14
0.74
21
Authors
4
Name
Order
Citations
PageRank
Davide Anguita1100170.58
Luca Carlino2140.74
Alessandro Ghio366735.71
Sandro Ridella4677140.62