Paper Info
Title
An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n)
Abstract
In this paper, the authors propose an efficient reconfigurable Montgomery multiplier for Galois prime field GF(n) that employs carry-save addition. The multiplier can operate for any operand length 'k' where 1\lek\leqslantN. The value of N determines the maximum operand length that the multiplier can support, which is application dependent. The value 'k' can be changed and hence can be configured and programmed. The final result can be obtained in 'k+1' clock cycles of operation after reset. The advantages of the proposed design are high order of flexibility, which allows easy reconfigurability for any operand length and low hardware complexity. The minimal area overhead to achieve reconfigurability is another major advantage. The critical path delay of the design is 6TXOR + TAND + T4:1MUX + T2:1MUX, where TXOR, TAND, T4:1MUX, and T2:1MUX are delays of 2-input XOR, 2-input AND, 4:1 multiplexer and 2:1 multiplexer respectively. To the best of our knowledge this appears to be the only reconfigurable architecture for Montgomery multiplication over Galois prime field. Further, clock and signal gating techniques have been employed for low-power consumption of the multiplier.
Year
DOI
Venue
2006
10.1109/DSD.2006.23
DSD
Keywords
Field
DocType
montgomery multiplier,maximum operand length,montgomery multiplication,efficient reconfigurable montgomery multiplier,easy reconfigurability,efficient reconfigurable,2-input xor,galois prime field,operand length,proposed design,clock cycle,galois fields,logic design,critical path,cryptography
Logic synthesis,Architecture,Finite field,Reconfigurability,Computer science,Cryptography,Operand,Parallel computing,Multiplier (economics),Multiplexer,Real-time computing
Conference
ISBN
Citations 
PageRank 
0-7695-2609-8
2
0.41
References 
Authors
5
3
Name
Order
Citations
PageRank
R. V. Kamala1121.39
M. Sudhakar2141.80
M. B. Srinivas39615.09