Name
Abstract | ||
|---|---|---|
The advancement in process technology has made it possible to integrate multiple processing modules on a single chip. As a result of this, there is a sharp increase of communication traffic on the communication bus architecture. In this case, the traditional single bus based architecture may fail to meet the real-time constraints. The major concern of the scaled technology is an effect of coupling capacitance due to the trend of shrinking pitches, i.e., the distance between two wires. Its consequence is higher crosstalk noise, which degrades the signal integrity and modifies the power consumption of the wires. This motivates the synthesis of a custom on-chip bus architecture, which is efficient in terms of power and performance. Further, the memory of a complex multiprocessor system has a significant contribution to power and delay.In this paper, we present a co-synthesis of on-chip buses and memories, which finds an optimal bus architecture, memory sizes, and the number of memories. The bus synthesis problem is formulated as an optimization problem as proposed in [11], [9]. Then it is solved efficiently using an optimization tool. The memory synthesis problem is based on the graph partitioning algorithm, which partitions a data dependency task graph into a set of sub graphs with the minimum number of data dependencies called cut. The experiments carried out on the real-life multimedia applications validate the proposed technique for the co-synthesis of bus architecture and memory. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/VLSISOC.2007.4402518 | VLSI-SOC 2007: PROCEEDINGS OF THE 2007 IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION |
Keywords | Field | DocType |
chip,optimization problem,real time,graph partitioning,signal integrity,capacitance,degradation,crosstalk | Physical address,Computer science,Address bus,Local bus,Memory bus,Back-side bus,System bus,Memory architecture,Control bus,Embedded system | Conference |
Citations | PageRank | References |
3 | 0.42 | 8 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sujan Pandey | 1 | 35 | 6.13 |
| Christian Genz | 2 | 28 | 3.15 |
| Rolf Drechsler | 3 | 3707 | 351.36 |