Name
Abstract | ||
|---|---|---|
Many-core tiled CMP proposals often assume a partially shared last level cache (LLC) since this provides a good compromise between access latency and cache utilization. In this paper, we propose a novel way to map memory addresses to LLC banks that takes into account the average distance between the banks and the tiles that access them. Contrary to traditional approaches, our mapping does not group the tiles in clusters within which all the cores access the same bank for the same addresses. Instead, two neighboring cores access different sets of banks minimizing the average distance travelled by the cache requests. Results for a 64-core CMP show that our proposal improves both execution time and the energy consumed by the network by 13% when compared to a traditional mapping. Moreover, our proposal comes at a negligible cost in terms of hardware and its benefits in both energy and execution time increase with the number of cores. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1145/2086696.2086704 | TACO |
Keywords | Field | DocType |
64-core cmp show,llc bank,cores access,last level cache,cache request,cache organization,cache utilization,neighboring cores access,access latency,average distance,many-core tiled cmp proposal,difference set,power,cache | Cache invalidation,Cache pollution,Cache,Computer science,Parallel computing,Real-time computing,Cache algorithms,Page cache,Cache coloring,Bus sniffing,Smart Cache,Distributed computing | Journal |
Volume | Issue | ISSN |
8 | 4 | 1544-3566 |
Citations | PageRank | References |
3 | 0.41 | 17 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Antonio Garcia-Guirado | 1 | 6 | 1.81 |
| Ricardo Fernández-Pascual | 2 | 9 | 2.31 |
| Alberto Ros | 3 | 384 | 32.60 |
| J. M. García | 4 | 588 | 58.90 |