Name
Abstract | ||
|---|---|---|
At advanced technology nodes, highly-optimized placements need careful post-processing to further reduce interconnect length or optimize resource distribution, and therefore, high-performance legalization and detailed placement steps are essential for performance. In the last decade, we observed impressive improvements both in quality and speed of academic placement algorithms, in part enabled by the availability of realistic benchmarks and common evaluation frameworks along the history of ISPD, DAC and ICCAD placement contests. However, most research innovations have heavily relied on improvement and extensions of global placement algorithms [4, 5, 8, 9, 12, 15]. Detailed placement has been often limited to mixing existing methods and local interconnect length recovery, and individual impacts and relative performances of different detailed placement algorithms remain unclear.
The goal of the ICCAD-2013 detailed-placement contest is to address these issues. In this contest, we provide (i) a suite of realistic benchmarks derived from industrial ASIC including input legal placements to detailed placers, and (ii) an evaluation framework to specifically measure the impact of detailed placement optimizations. To judge the quality of resulting placements, we consider both Half-Perimeter Wirelength (HPWL) and placement density, and impose maximum cell displacement limitations to the detailed placers. We hope that a set of standardized benchmarks and an evaluation framework will further accelerate research in the area of detailed placement.
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Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ICCAD.2013.6691130 | ICCAD |
Keywords | Field | DocType |
detailed placement optimizations,detailed placement step,evaluation framework,detailed placement,benchmark suite,academic placement algorithm,iccad-2013 cad contest,iccad placement contest,global placement algorithm,realistic benchmarks,detailed placers,different detailed placement algorithm,integrated circuit design,algorithms,physical design,optimization,placement,vlsi | CAD,Suite,Computer science,CONTEST,Electronic engineering,Placement,Application-specific integrated circuit,Real-time computing,Integrated circuit design,Physical design,Very-large-scale integration | Conference |
ISSN | ISBN | Citations |
1933-7760 | 978-1-4799-1069-4 | 12 |
PageRank | References | Authors |
0.66 | 16 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Myung-Chul Kim | 1 | 665 | 57.05 |
| Natarajan Viswanathan | 2 | 538 | 28.41 |
| Zhuo Li | 3 | 387 | 20.61 |
| Charles Alpert | 4 | 73 | 3.12 |