Name
Title | ||
|---|---|---|
TurboVG: a HW/SW co-designed multi-core openVG accelerator for vector graphics applications with embedded power profiler |
Abstract | ||
|---|---|---|
TurboVG is a hardware accelerator for the OpenVG 1.1 library that operates sixteen times faster than an optimized software implementation. This improved efficiency stems from a well-designed hardware-software interaction capable of handling massive data transfers across hierarchical layers without performance loss. By combining multiple TurboVG cores, the library can support screen resolutions of up to Full-HD 1080p.
|
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ASPDAC.2011.5722315 | ASP-DAC |
Keywords | Field | DocType |
performance loss,hierarchical layer,vector graphics application,massive data transfer,embedded power profiler,sixteen time,multi-core openvg accelerator,improved efficiency,screen resolution,hardware accelerator,optimized software implementation,multiple turbovg core,graphics,central processing unit,data transfer,field programmable gate arrays,field programmable gate array,hardware | Graphics,Power management,Central processing unit,Vector graphics,Computer science,Field-programmable gate array,Software,Hardware acceleration,Multi-core processor,Embedded system | Conference |
ISSN | ISBN | Citations |
2153-6961 | 978-1-4244-7516-2 | 1 |
PageRank | References | Authors |
0.41 | 2 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shuo-Hung Chen | 1 | 4 | 1.20 |
| Hsiao-Mei Lin | 2 | 4 | 1.20 |
| Ching-Chou Hsieh | 3 | 1 | 0.75 |
| Chih-Tsun Huang | 4 | 673 | 54.07 |
| Jing-Jia Liou | 5 | 552 | 64.27 |
| Yeh-Ching Chung | 6 | 983 | 97.16 |