Paper Info
Title
Instruction scheduling of VLIW architectures for balanced power consumption
Abstract
An instruction word in VLIW (very long instruction word) processors consists of a variable number of individual instructions. Therefore the power consumption variation over time significantly depends on the parallel instruction schedule generated by the compiler. Sharp power variations across time cause power supply noises, degrade chip reliability and accelerate battery exhaustion. This paper proposes a branch and bound algorithm for instruction scheduling of VLIW architectures that effectively minimizing power variation without degrading the speed. Our experimental results demonstrate the efficiency of our algorithm compared with previously presented approaches. Finally, a new rough sets based approach to the instruction-level VLIW power model for this instruction scheduling optimization problem is discussed.
Year
DOI
Venue
2005
10.1109/ASPDAC.2005.1466470
ASP-DAC
Keywords
Field
DocType
instruction scheduling,instruction word,optimisation,rough set theory,processor scheduling,long instruction word,vliw architecture,branch and bound algorithm,parallel instruction schedule,power consumption variation,parallel architectures,individual instruction,instruction scheduling optimization problem,rough sets,power variation minimization,instruction sets,power variation,vliw architectures,instruction-level vliw power model,balanced power consumption,very long instruction word processors,sharp power variation,chip,optimization problem,very long instruction word,rough set,reliability,performance,link
Branch and bound,Instruction scheduling,Very long instruction word,Instruction set,Computer science,Parallel computing,Rough set,Real-time computing,Compiler,Chip,Optimization problem
Conference
Volume
ISSN
ISBN
2
2153-6961
0-7803-8736-8
Citations 
PageRank 
References 
1
0.35
12
Authors
2
Name
Order
Citations
PageRank
Shu Xiao14013.46
Edmund M. -K. Lai2555.44