Title
A new framework to accelerate Virtex-II Pro dynamic partial self-reconfiguration
Abstract
The Xilinx Virtex family of FPGAs provides the ability to perform partial run-time reconfiguration, also known as dynamic partial reconfiguration (DPR). Taking this concept one step further, partial dynamic self-reconfiguration becomes possible through the internal configuration access port (ICAP). In this paper a framework for lowering reconfiguration times using the combitgen tool to reduce the overhead found within bitstreams, along with a completely new, very simple and area efficient ICAP controller that is connected directly to the processor local bus (PLB) and is equipped with direct memory access (DMA) capabilities is presented. Using this PLB Master ICAP controller, it is possible to reach the maximum practical throughput that can be achieved with the ICAP interface of Virtex-II Pro devices. Compared to an alternative realization using the OPBHWICAP provided by Xilinx (a slave attachment on the on-chip peripheral bus), it is possible to achieve improvements concerning reconfiguration times by a factor of 20.
Year
DOI
Venue
2007
10.1109/IPDPS.2007.370362
IPDPS
Keywords
Field
DocType
reconfiguration time,dynamic partial self-reconfiguration,virtex-ii pro dynamic partial self-reconfiguration,internal configuration access port interface,system-on-chip,system buses,combitgen tool,logic design,on-chip peripheral bus,fpga,icap,direct memory access,field programmable gate arrays,processor local bus,hardware,switches,image processing,system on chip,coprocessors,throughput,acceleration,chip,system on a chip
Logic synthesis,System on a chip,Peripheral bus,Computer science,Parallel computing,Field-programmable gate array,Direct memory access,Local bus,Virtex,Control reconfiguration,Embedded system
Conference
ISBN
Citations 
PageRank 
1-4244-0910-1
31
3.40
References 
Authors
10
4
Name
Order
Citations
PageRank
Christopher Claus122120.39
Florian Helmut Müller2364.84
Johannes Zeppenfeld310410.19
Walter Stechele436552.77