Name
Abstract | ||
|---|---|---|
Circuit-switched networks provide guaranteed transmission latency and throughput, and hence are suitable for many network-on-chip (NoC) architectures requiring quality-of-service. A circuit-switched on-chip network needs a scheduler to arrange communication paths and allocate a proper bandwidth for each path. Such a scheduler offers an effective solution for a critical step in the NoC design. In this paper, we propose an efficient scheduler for pre-scheduled circuit-switched on-chip networks. Based on simulations, we show that low delivery latency for circuit-switched on-chip networks can be achieved with our scheduler. Furthermore, with efficient scheduling, the cost of the switches can be also minimized |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/VLSISOC.2006.313206 | VLSI-SOC |
Keywords | DocType | ISBN |
network-on-chip architectures,quality-of-service,noc design,quality of service,scheduler,circuit-switched networks,switched networks,network-on-chip,circuit switched,chip,network on chip | Conference | 3-901882-19-7 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsin-Chou Chi | 1 | 38 | 6.97 |
| Chia-Ming Wu | 2 | 59 | 6.42 |