Title
A 1.8-GHz instruction window buffer for an out-of-order microprocessor core
Abstract
To address the challenges in microprocessor designs beyond a gigahertz, an instruction window buffer (IWB) was designed. The IWB implements the processor parts for renaming, reservation station, and reorder buffer as a unified buffer. Measured results on an experimental chip demonstrated operation of the IWB macros supporting 1.8 GHz, with the chip being at the fast end of the process distribution...
Year
DOI
Venue
2001
10.1109/4.962282
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Out of order,Microprocessors,Microarchitecture,CMOS technology,Integrated circuit technology,High speed integrated circuits,Semiconductor device measurement,Integrated circuit measurements,Copper,Integrated circuit interconnections
Journal
36
Issue
ISSN
Citations 
11
0018-9200
8
PageRank 
References 
Authors
0.62
7
6
Name
Order
Citations
PageRank
J. Leenstra1564.45
J. Pille2192.21
A. Muller3111.20
W. M. Sauer41278.79
R. Sautter580.62
D. F. Wendel6555.87