Title
A Dynamic Core Grouping Approach to Improve Raw Architecture Many-core Processor Performance
Abstract
The ongoing move of hardware platforms to many-core processor challenges the traditional software design methodology. It is critical to develop new programming paradigms and efficient ways to port legacy applications. This paper analyzed a typical packet processing application and also the cache hierarchy and behavior of Raw architecture many-core processor. It presented an easy to implement run-time dynamic core grouping approach to improve the system performance. This approach reduced the cache swap latency by grouping neighbor cores attached to the mesh network. It optimized the scale of group by experimental data got beforehand. The test results showed this approach can improve the Deep Packet Inspection (DPI) system performance around 10% with very minor code change.
Year
DOI
Venue
2011
10.1109/PARELEC.2011.30
PARELEC
Keywords
Field
DocType
hardware platforms,software design methodology,deep packet inspection,dynamic core grouping approach,processor performance,parallel architectures,hardware platform,raw architecture many-core processor,mesh network,system performance,experimental data,multiprocessing systems,programming paradigms,deep packet inspection system,packet processing application,grouping neighbor core,core grouping,many-core processor,efficient way,cache swap latency,raw architecture many-core processor performance,performance evaluation,packet processing,run-time dynamic core grouping approach,improve raw architecture many-core,legacy applications,cache hierarchy,hardware,inspection,computer architecture,software design,throughput,mesh networks,programming paradigm
Deep packet inspection,Computer architecture,Software design,Programming paradigm,Cache,Computer science,Parallel computing,Packet processing,Throughput,Multi-core processor,Legacy system
Conference
ISBN
Citations 
PageRank 
978-0-7695-4397-0
0
0.34
References 
Authors
2
1
Name
Order
Citations
PageRank
Zhitao Wan1124.34